This invention relates, in general, to non-volatile memory structures and more particularly to a novel electrically alterable floating gate injected device.
The computer and related art have long required read-only memory (ROM) elements that were non-volatile and the prior art has provided many devices which, to some extent, have tempted to fill this need to varying degrees. However, since the computer art has progressed in complexity there now exists a need to provide electrically alterable read-only memories that may be programmed (or "written") and, if the occasion arises to reprogram (erase and write) in the field. To this end, devices are presently available that exhibit non-volatile characteristics but, as will be discussed, they each have inherent shortcomings that are overcome by the subject invention.
At one end of the spectrum of semiconductor memory devices is the family of Floating gate-Avalanche-Metal-Oxide Semiconductor (FAMOS) devices while the other end of the spectrum is represented by the family of Metal-Nitride-Oxide Semiconductor (MNOS) devices. The advantages of each type of device resides in the fact that they are independent of any outside power (current or voltage) to maintain the stored information in the event power is lost, and since they are independent of any outside power, there is no need for any further refreshing of the device. Hence, there is a significant saving in the power necessary to operate the device.
The floating gate family of devices usually has source and drain regions of one conductivity formed in a substrate of the opposite conductivity, at the surface thereof. Between the source and the drain regions, and on the surface of the substrate, a gate structure is created by first forming a thin oxide layer on the surface of the substrate between the source and the drain regions (the channel region). A conductive layer is then placed over the insulating layer and constitutes the floating gate. A second insulating layer is then formed over the floating gate to completely surround the floating gate and insulate it from the remainder of the device followed by a second conductive layer (the control gate) which is formed atop the second insulating layer. Such floating gate devices, which are exemplified in U.S. Pat. Nos. 3,500,142 and 3,755,721, have inherent drawbacks in that high fields are required to produce the necessary avalanche breakdown from the substrate to the floating gate so that a charge will appear on the floating gate. Further, to erase the charge trapped on the floating gate, the entire device is usually flooded with energy in the ultraviolet or x-ray portion of the spectrum. Thus, it is extremely difficult, bordering on the impossible, to erase a single "word" without erasing all the charge on the remainder of the device, thereby requiring the device to be completely reprogrammed. However, other serious defects are manifest in both FAMOS and MNOS devices. For example, both prior art type devices show a marked tendency toward zener breakdown at the drain-substrate junction particularly at high voltages. Further, since charge is placed on the floating gate (and nitride layer) by means of electrons or holes flowing through the thin layer of gate oxide material it has been found that after relatively few charge and discharge (write and erase) cycles has been accomplished, the user is faced with a radical change in the threshold voltage of the device, a situation which, in many instances, may require the replacement of the device. It is theorized that the holes and electrons during transit through the thin gate oxide layer disrupts the layer to the extent that the threshold voltage is markedly raised.